Silicon-germanium (SiGe) virtual substrates are a platform for new generations of very large scale integration (VLSI) devices that exhibit enhanced performance in comparison to devices fabricated on bulk Si substrates. An important component of a SiGe virtual substrate is a layer of SiGe that has been relaxed to its equilibrium lattice constant (i.e., one that is larger than that of Si). This relaxed SiGe layer may be formed directly on a Si substrate (e.g., by wafer bonding or direct epitaxy) or atop a relaxed graded SiGe layer, in which the lattice constant of the SiGe material has been increased gradually over the thickness of the layer. The SiGe virtual substrate can also incorporate buried insulating layers, echoing the structure of a semiconductor-on-insulator (SOI) wafer. In order to fabricate high performance devices on these platforms, thin strained semiconductor layers of Si, Ge, or SiGe are grown on the relaxed SiGe virtual substrates. The resulting biaxial tensile or compressive strain alters carrier mobilities in these layers, enabling the fabrication of high speed and/or low power devices.
Differences in lattice constants of various materials may result in misfit dislocations forming at an interface between the thin strained semiconductor layer, such as strained Si and an underlying layer, such as relaxed SiGe.
Misfit dislocations form when an upper strained semiconductor layer reaches a critical thickness Tcrit. This equilibrium critical thickness is a not a function of temperature, but at reduced temperatures, strained layers may be grown in a metastable state. The metastable thickness of the strained layer may be thicker than Tcrit, but misfit dislocations may not have formed because of the absence of sufficient thermal energy for their formation. The metastable critical thickness of a strained layer is larger than Tcrit, and decreases with increasing temperature. At temperatures commonly used for complementary metal-oxide semiconductor (CMOS) processing, the metastable critical thickness of a typical upper strained semiconductor layer is close to Tcrit. The critical thickness of a strained layer utilized in CMOS devices and processed at elevated temperatures may be therefore considered the equilibrium critical thickness Tcrit.
One may avoid the formation of misfit dislocations in, e.g., CMOS devices by keeping the thickness of the upper strained semiconductor layer much less than Tcrit. This approach, however, places severe constraints on CMOS design rules. In addition, the close proximity of an underlying semiconductor layer containing, for example, SiGe to a top surface of the wafer creates a number of process optimization challenges, such as the definition of source and drain junctions, formation of metal silicides, and fabrication of shallow-trench-isolation (STI) regions. Optimization of these design features is complicated by interaction with, e.g., both Si and Ge.
Alternatively, one may distance misfit dislocations from an upper strained semiconductor layer by, e.g., forming the upper strained semiconductor layer with a thickness much greater than a critical thickness for misfit dislocation formation. Then, however, the misfit dislocations—even though concentrated away from the top surface of the strained layer—may cause problems in devices, such as MOSFETs, fabricated in this layer. Because the density of misfit dislocations increases as layer thickness increases above Tcrit, this solution may create a high density of misfit dislocations at an interface between the strained layer and the underlying layer. Misfit dislocations may act as diffusion pipes, facilitating migration of dopants between sources and drains, thereby promoting leakage. Misfit dislocations may also act as carrier recombination/generation centers in which electrons and holes combine, thereby also promoting leakage. Further, non-uniform distribution of misfit dislocations may introduce spatial variations in strain across the surface of the wafer. Moreover, making the upper strained semiconductor layer too thick may result in the relaxation of the layer, thereby negating the increase in carrier mobility provided by a strained layer.